FW82801EB Intel, FW82801EB Datasheet - Page 60

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.12
60
Table 14. Processor Interface Signals (Sheet 1 of 2)
Processor Interface
CPUSLP#
STPCLK#
IGNNE#
FERR#
A20M#
Name
INIT#
INTR
SMI#
NMI
Type
O
O
O
O
O
O
O
O
I
Mask A20: A20M# will go active based on either setting the appropriate bit in the
Port 92h register, or based on the A20GATE input being active.
Speed Strap: During the reset sequence, the Intel
corresponding bit is set in the FREQ_STRP register.
CPU Sleep: This signal puts the processor into a state that saves substantial power
compared to Stop-Grant state. However, during that time, no snoops occur. The
ICH5 can optionally assert the CPUSLP# signal when going to the S1 state.
Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on
the processor. FERR# is only used if the ICH5 coprocessor error reporting function is
enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If
FERR# is asserted, the ICH5 generates an internal IRQ13 to its interrupt controller
unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted
to the processor unless FERR# is active. FERR# requires an external weak pull-up
to ensure a high level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the processor of
Ignore Numeric Error: This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the ICH5 coprocessor error reporting function is
enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If
FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error
Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until
FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is
written, the IGNNE# signal is not asserted.
Speed Strap: During the reset sequence, ICH5 drives IGNNE# high if the
corresponding bit is set in the FREQ_STRP register.
Initialization: INIT# is asserted by the ICH5 for 16 PCI clocks to reset the processor.
ICH5 can be configured to support processor BIST. In that case, INIT# will be active
when PCIRST# is active.
CPU Interrupt: INTR is asserted by the ICH5 to signal the processor that an
interrupt request is pending and needs to be serviced. It is an asynchronous output
and normally driven low.
Speed Strap: During the reset sequence, ICH5 drives INTR high if the
corresponding bit is set in the FREQ_STRP register.
Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the
processor. The ICH5 can generate an NMI when either SERR# or IOCHK# is
asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is
reset by setting the corresponding NMI source enable/disable bit in the NMI Status
and Control Register.
Speed Strap: During the reset sequence, ICH5 drives NMI high if the corresponding
bit is set in the FREQ_STRP register.
System Management Interrupt: SMI# is an active low output synchronous to
PCICLK. It is asserted by the ICH5 in response to one of many enabled hardware or
software events.
Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It
is asserted by the ICH5 in response to one of many hardware or software events.
When the processor samples STPCLK# asserted, it responds by stopping its internal
clock.
pending interrupt events. This functionality is independent of the General
Control Register bit setting.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Description
®
ICH5 drives A20M# high if the