FW82801EB Intel, FW82801EB Datasheet - Page 389

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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9.10.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PM1_CNT—Power Management 1 Control
I/O Address:
Default Value:
Lockable:
Power Well:
15:14
12:10
Bit
9:3
13
2
1
0
Reserved.
Sleep Enable ( SLP_EN) — WO. Setting this bit causes the system to sequence into the Sleep
state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system should enter
when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
000 = ON: Typically maps to S0 state.
001 = it asserts STPCLK#. Puts processor in Stop-Grant state. Optional to assert CPUSLP# to put
010 = Reserved
011 = Reserved
100 = Reserved
101 = Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
110 = Suspend-To-Disk. Assert SLP_S3# and SLP_S4#: Typically maps to S4 state.
111 = Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state.
Reserved.
Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a
Reserved
SCI Enable ( SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for various events
including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
corresponding enable and status bits to control its ability to receive ACPI events.
processor in sleep state: Typically maps to S1 state.
PMBASE + 04h
( ACPI PM1a_CNT_BLK )
0000h
No
Bits 0
Bits 8
Bits 13
7: Core,
12: RTC,
15: Resume
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Usage:
R/W, WO
32-bit
ACPI or Legacy
389

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