FW82801EB Intel, FW82801EB Datasheet - Page 618

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Electrical Characteristics
618
Table 195. Power Management Timings
NOTES:
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2. This transition is clocked off the 66 MHz CLK66. 1 CLK66 is approximately 15 ns.
3. The ICH5 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
5. The ICH5 has no maximum timing requirement for this transition. It is up to the system designer to determine
6. If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
8. This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 µs).
9. For timing t198d, the Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width”
t183a SLPS5# inactive to SLP_S4# inactive
t183b SLPS4# inactive to SLP_S3# inactive
t194a SLP_S3# active to SLP_S4# active
t198a Wake Event to SLP_S4# inactive(S4 Wake)
t198b S3 Wake Event to SLP_S3# inactive(S3 Wake)
t198d
t198e SLP_S4# inactive to SLP_S3# inactive
Sym
t181
t182
t183
t184
t185
t186
t187
t188
t189
t190
t192
t193
t194
t195
t196
t197
t198
t220
for this cycle getting to the ICH5 is dependant on the processor and the memory controller.
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
together similar to timing t194 (PCIRST# active to SLP_S3# active).
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
and the “SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).
VccSus active to SLP_S5#, SUS_STAT# and PCIRST#
active
RSMRST# inactive to SUSCLK running, SLP_S5#
inactive
Vcc active to STPCLK# and CPUSLP# inactive, and
Processor Frequency Strap signals high
PWROK and VRMPWRGD active and SYS_RESET#
inactive to SUS_STAT# inactive and Processor
Frequency Straps latched to Strap Values
Processor Reset Complete to Frequency Strap signals
unlatched from Strap Values
STPCLK# active to Stop Grant cycle
Stop Grant cycle to CPUSLP# active
S1 Wake Event to CPUSLP# inactive
CPUSLP# inactive to STPCLK# inactive
CPUSLP# active to SUS_STAT# active
SUS_STAT# active to PCIRST# active
PCIRST# active to SLP_S3# active
SLP_S4# active to SLP_S5# active
SLP_S3# active to PWROK, VRMPWRGD inactive
PWROK, VRMPWRGD inactive to Vcc supplies inactive
Wake Event to SLP_S5# inactive
SLP_S5# inactive or S4 Wake Event to SLP_S4#
inactive
THRMTRIP# active to SLP_S3#, SLP_S4#, SLP_S5#
active
Parameter
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
3.87
Min
N/A
32
60
20
1
1
7
1
2
9
1
1
1
0
1
1
0
1
See Note Below
Max
110
N/A
245
50
50
38
63
25
21
10
10
2
2
9
4
2
2
2
2
2
3
RTCCLK
RTCCLK
RTCCLK 1
RTCCLK 1
RTCCLK 1
RTCCLK 1
RTCCLK 1
RTCCLK 1, 6
RTCCLK 1
RTCCLK 1
RTCCLK 1
RTCCLK 1
PCI CLK
PCICLK
PCICLK
CLK66
Units
ms
ms
ns
ns
µs
ns
7
2
3
4
4
5
9
Notes
21
21
21
21
21
23
21
21
22
22
23
22
22
23
23
23
23
23
23
23
23
Fig