FW82801EB Intel, FW82801EB Datasheet - Page 180

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16.2.6
5.16.2.7
180
Table 77. Interrupt/Active Bit Interaction Definition
Error Conditions
The buffer is flushed (when in the write state) or invalidated (when in the read state) when a
terminal count condition exists; that is, the current region descriptor has the EOL bit set and that
region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when
the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register
and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured
that all data destined for system memory has been transferred and that data is valid in system
memory.
after a DMA transfer has started.
During concurrent DMA or Ultra ATA transfers, the ICH5 IDE interface arbitrate between the
primary and secondary IDE cables when a PRD expires.
IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis;
either a sector is transferred successfully or it is not. A sector is 512 bytes.
If the IDE device does not complete the transfer due to a hardware or software error, the command
will eventually be stopped by the driver setting Command Start bit to 0 when the driver times out
the disk transaction. Information in the IDE device registers help isolate the cause of the problem.
If the controller encounters an error while doing the bus master transfers it will stop the transfer
(i.e., reset the Active bit in the Command register) and set the Error bit in the Bus Master IDE
Status register. The controller does not generate an interrupt when this happens. The device driver
can use device specific information (PCI Configuration Space Status register and IDE Drive
Register) to determine what caused the error.
Whenever a requested transfer does not complete properly, information in the IDE device registers
(Sector Count) can be used to determine how much of the transfer was completed and to construct
a new PRD table to complete the requested operation. In most cases the existing PRD table can be
used to complete the operation.
8237-Like Protocol
The 8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins
familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/write strobes.
These pins have similar characteristics to their ISA counterparts in terms of when data is valid
relative to strobe edges, and the polarity of the strobes, however the ICH5 does not use the 8237 for
this mode.
Interrupt
0
1
1
0
Table 77
Active
1
0
1
0
describes how to interpret the Interrupt and Active bits in the Status Register
DMA transfer is in progress. No interrupt has been generated by the IDE device.
The IDE device generated an interrupt. The controller exhausted the Physical
Region Descriptors. This is the normal completion case where the size of the
physical memory regions was equal to the IDE device transfer size.
The IDE device generated an interrupt. The controller has not reached the end of the
physical memory regions. This is a valid completion case where the size of the
physical memory regions was larger than the IDE device transfer size.
This bit combination signals an error condition. If the Error bit in the status register is
set, then the controller has some problem transferring data to/from memory.
Specifics of the error have to be determined using bus-specific information. If the
Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Description