FW82801EB Intel, FW82801EB Datasheet - Page 106

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.4.1.5
5.4.1.6
5.4.1.7
106
Table 37. SYNC Bit Definition
Table 38. Intel
SYNC Error Indication
SYNC
Valid values for the SYNC field are shown in
NOTE: All other combinations are RESERVED.
SYNC Time-Out
There are several error cases that can occur on the LPC interface.
and the ICH5 response.
There may be other peripheral failure conditions; however, these are not handled by the ICH5.
The SYNC protocol allows the peripheral to report an error via the LAD[3:0] = 1010b encoding.
The intent of this encoding is to give peripherals a method of communicating errors to aid higher
layers with more robust error recovery.
If the ICH5 was reading data from a peripheral, data will still be transferred in the next two nibbles.
This data may be invalid, but it must be transferred by the peripheral. If the ICH5 was writing data
to the peripheral, the data had already been transferred.
Intel
SYNC after 4 consecutive clocks. This could occur if the processor tries to
access an I/O location to which no device is mapped.
ICH5 drives a Memory, I/O, or DMA cycle, and a peripheral drives more than 8
consecutive valid SYNC to insert wait-states using the Short (0101b) encoding
for SYNC. This could occur if the peripheral is not operating properly.
ICH5 starts a Memory, I/O, or DMA cycle, and a peripheral drives an invalid
SYNC pattern. This could occur if the peripheral is not operating properly or if
there is excessive noise on the LPC I/F.
Bits[3:0]
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®
0000
0101
0110
1001
1010
ICH5 starts a Memory, I/O, or DMA cycle, but no device drives a valid
ICH5 Response to Sync Failures
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request
deassertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the Intel
this encoding. Instead, the ICH5 uses the Long Wait encoding (see next encoding below).
Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding
driven by the ICH5 for bus master cycles, rather than the Short Wait (0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and
more DMA transfers desired to continue after this transfer. This value is valid only on DMA
transfers and is not allowed for any other type of cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK#
signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious
error in this transfer. For DMA transfers, this not only indicates an error, but also indicates
DMA request deassertion and no more transfers desired for that channel.
Possible Sync Failure
Table
Intel
37.
®
Indication
82801EB ICH5 / 82801ER ICH5R Datasheet
Table 38
ICH5 aborts the cycle after
the fourth clock.
Continues waiting
ICH5 aborts the cycle when
the invalid Sync is
recognized.
indicates the failing case
Intel
®
®
ICH5 does not use
ICH5 Response