FW82801EB Intel, FW82801EB Datasheet - Page 175

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.16.1.2
Intel
®
Table 75. IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The Data Register (I/O Offset 00h) should be accessed using 16-bit or 32-bit I/O instructions. All
IDE Legacy Mode and Native Mode
The ICH5 IDE controller supports both legacy mode and PCI native mode. In legacy mode, the
Command and Control Block registers are accessible at fixed I/O addresses. While in legacy mode,
the ICH5 does not decode any of the native mode ranges. Likewise, in native mode the ICH5 does
not decode any of the legacy mode ranges.
The IDE I/O ports involved in PIO transfers are decoded by the ICH5 to the IDE interface when
D31:F1 I/O space is enabled and IDE decode is enabled through the IDE_TIMx registers. The IDE
registers are implemented in the drive itself. An access to the IDE registers results in the assertion
of the appropriate IDE chip select for the register, and the IDE command strobes (PDIOR#/
SDIOR#, PDIOW#/SDIOW#).
There are two I/O ranges for each IDE cable: the Command Block, which corresponds to the
PCS1#/SCS1# chip select, and the Control Block, which corresponds to the PCS3#/SCS3# chip
select. The Command Block is an 8-byte range, while the control block is a 4-byte range.
Table 75
other registers should be accessed using 8-bit I/O instructions.
NOTE: For accesses to the Alt Status register in the Control Block, the ICH5 must always force the upper
In native mode, the ICH5 does not decode the legacy ranges. The same offsets are used as in
Table
locations.
I/O Offset
— Command Block Offset: 01F0h for Primary, 0170h for Secondary
— Control Block Offset: 03F4h for Primary, 0374h for Secondary
75. However, the base addresses are selected using the PCI BARs, rather than fixed I/O
00h
01h
02h
03h
04h
05h
06h
07h
address bit (PDA2 or SDA2) to 1 in order to guarantee proper native mode decode by the IDE device.
Unlike the legacy mode fixed address location, the native mode address for this register may contain a 0
in address bit 2 when it is received by the ICH5.
specifies the registers as they affect the ICH5 hardware definition.
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive
Status
Register Function
(Read)
Data
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Head
Command
Register Function
(Write)
Functional Description
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