FW82801EB Intel, FW82801EB Datasheet - Page 224
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FW82801EB
Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet
1.FW82801EB.pdf
(671 pages)
Specifications of FW82801EB
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Functional Description
5.20.8.2
224
Device Connects
The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0
describes the details of handling Device Connects in Section 4.2. There are four general scenarios
that are summarized below.
1. Configure Flag = 0 and a full speed/low speed-only Device is connected
2. Configure Flag = 0 and a high speed-capable Device is connected
3. Configure Flag = 1 and a full speed/low speed-only Device is connected
4. Configure Flag = 1 and a high speed-capable Device is connected
— In this case, the UHC is the owner of the port both before and after the connect occurs.
— In this case, the UHC is the owner of the port both before and after the connect occurs.
— In this case, the EHC is the owner of the port before the connect occurs. The EHCI driver
— In this case, the EHC is the owner of the port before, and remains the owner after, the
The EHC (except for the port-routing logic) never sees the connect occur. The UHCI
driver handles the connection and initialization process.
The EHC (except for the port-routing logic) never sees the connect occur. The UHCI
driver handles the connection and initialization process. Since the UHC does not perform
the high-speed chirp handshake, the device operates in compatible mode.
handles the connection and performs the port reset. After the reset process completes, the
EHC hardware has cleared (not set) the Port Enable bit in the EHC’s PORTSC register.
The EHCI driver then writes a 1 to the Port Owner bit in the same register, causing the
UHC to see a connect event and the EHC to see an “electrical” disconnect event. The
UHCI driver and hardware handle the connection and initialization process from that
point on. The EHCI driver and hardware handle the perceived disconnect.
connect occurs. The EHCI driver handles the connection and performs the port reset.
After the reset process completes, the EHC hardware has set the Port Enable bit in the
EHC’s PORTSC register. The port is functional at this point. The UHC continues to see an
unconnected port.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
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