FW82801EB Intel, FW82801EB Datasheet - Page 450

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SATA Controller Registers (D31:F2)
11.1.29
11.1.30
11.1.31
450
MC—Message Signaled Interrupt Message Control
Register (SATA–D31:F2)
Address Offset:
Default Value:
MA—Message Signaled Interrupt Message Address
Register (SATA–D31:F2)
Address Offset:
Default Value:
MD—Message Signaled Interrupt Message Data Register
(SATA–D31:F2)
Address Offset:
Default Value:
Bits
15:8
Bits
31:2
Bits
15:0
6:4
3:1
1:0
7
0
Reserved
64 Bit Address Capable (C64) — RO. Hardwired to 0 to indicate capability of generating 32-bit
message only.
Multiple Message Enable (MME) — R/W. These bits are R/W for software compatibility, but only
one message is ever sent by Intel
Multiple Message Capable (MMC) — RO. Only one message is required.
MSI Enable (MSIE) — R/W.
0 = Disabled.
1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.
Address (ADDR) — R/W. Lower 32 bits of the system specified message address, always DWord
aligned.
Reserved
Data (DATA) — R/W. This field is programmed by system software if MSI is enabled. Its content is
driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI memory write
transaction.
82
0000h
84
00000000h
88
0000h
–
–
–
83h
87h
89h
®
ICH5.
Description
Intel
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO, R/W
16 bits
R/W
32 bits
R/W
16 bits