FW82801EB Intel, FW82801EB Datasheet - Page 115

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.6.3
5.6.4
5.6.5
Intel
®
Table 41. DMA Cycle vs. I/O Address
Table 42. PCI Data Bus vs. DMA I/O Port Size
Table 43. DMA I/O Cycle Width vs. BE[3:0]#
82801EB ICH5 / 82801ER ICH5R Datasheet
The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses
(Table
device.
DMA Addresses
The memory portion of the cycle generates a PCI memory read or memory write bus cycle, its
address representing the selected memory. The I/O portion of the DMA cycle generates a PCI
I/O cycle to one of the four I/O addresses listed in
DMA Data Generation
The data generated by PC/PCI devices on I/O reads when they have an active GNT# is on the lower
two bytes of the PCI AD bus.
channels. Each I/O read results in one memory write, and each memory read results in one
I/O write. If the I/O device is 8 bit, the ICH5 performs an 8-bit memory write. The ICH5 does not
assemble the I/O read into a DWord for writing to memory. Similarly, the ICH5 does not
disassemble a DWord read from memory to the I/O device.
DMA Byte Enable Generation
The byte enables generated by the ICH5 on I/O reads and writes must correspond to the size of the
I/O device.
NOTE: For verify cycles the value of the Byte Enables (BEs) is a “don’t care.”
DMA Cycle Type
PCI DMA I/O Port Size
41). Note that these cycles must be qualified by an active GNT# signal to the requesting
Normal TC
Verify TC
Normal
Verify
Table 43
BE[3:0]#
1100b
1110b
Word
Byte
defines the byte enables asserted for 8- and 16-bit DMA cycles.
DMA I/O Address
Table 42
0C0h
0C4h
00h
04h
16-bit DMA I/O Cycle: Channels 5–7
8-bit DMA I/O Cycle: Channels 0–3
lists the PCI pins that the data appears on for 8- and 16-bit
PCI Data Bus Connection
Description
AD[15:0]
AD[7:0]
Table
PCI Cycle Type
I/O Read/Write
I/O Read/Write
41.
I/O Read
I/O Read
Functional Description
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