FW82801EB Intel, FW82801EB Datasheet - Page 484

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.1.9
13.1.10
13.1.11
484
PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Reset:
31:10
15:0
Bit
7:0
Bit
9:4
2:1
Bit
3
0
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI controller is
internally implemented with arbitration via hub interface (and not PCI), it does not need a master
latency timer.
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10], respectively.
This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
Reserved
Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.
Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere within 32-bit
address space.
Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address field in this
register maps to memory space.
Subsystem Vendor ID (SVID) — R/W (special). This register, in combination with the USB 2.0
Subsystem ID register, enables the operating system to distinguish each subsystem from the others.
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (offset 80h, bit 0) is set to 1.
0Dh
00h
10
00000000h
2C
XXXXh
None
–
–
13h
2Dh
Description
Intel
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
8 bits
R/W, RO
32 bits
R/W (special)
16 bits