FW82801EB Intel, FW82801EB Datasheet - Page 258

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.22.2.10
5.22.2.11
5.22.2.12
5.22.2.13
258
Output Slot 9: Playback Sub Woofer Channel
Output Slot 12: I/O Control
AC-Link Input Frame (SDIN)
When set for 6-channel mode, this slot is used for the Sub Woofer. The format is the same as Slot 3.
If not set up for 6-channel mode, this channel is always stuffed with 0s by ICH5.
Output Slots 10–11: Reserved
Output frame slots 10
controller.
The 16 bits of DAA and GPIO control (output) and status (input) have been directly assigned to
bits on slot 12 to minimize latency of access to changing conditions.
The value of the bits in this slot are the values written to the GPIO control register at offset 54h and
D4h (in the case of a secondary codec) in the modem codec I/O space. The following rules govern
the usage of slot 12.
There are three AC_SDIN lines on the ICH5 for use with up to three codecs. Each AC_SDIN pin
can have a codec attached. The input frame data streams correspond to the multiplexed bundles of
all digital input data targeting the AC ’97 controller. As in the case for the output frame, each
AC-link input frame consists of twelve time slots.
A new audio input frame begins with a low to high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of AC_BIT_CLK. On the immediately following falling edge of
AC_BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks the time
when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of
AC_BIT_CLK, the codec transitions AC_SDIN into the first bit position of slot 0 (codec ready
bit). Each new bit position is presented to AC-link on a rising edge of AC_BIT_CLK, and
subsequently sampled by the ICH5 on the following falling edge of AC_BIT_CLK. This sequence
ensures that data transitions and subsequent sample points for both incoming and outgoing data
streams are time aligned.
AC_SDIN data stream must follow the AC ’97 v2.3 Specification and be MSB justified with all
non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s. AC_SDIN data
is sampled by the ICH5 on the falling edge of AC_BIT_CLK.
1. Slot 12 is marked invalid by default on coming out of AC-link reset, and remains invalid until
2. A write to offset 54h/D4h in codec I/O space causes the write data to be transmitted on slot 12
3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames. The data
4. Slot 12 gets invalidated after the following events: PCI reset, AC ’97 cold reset, warm reset,
a register write to 54h/D4h.
in the next frame, with slot 12 marked valid, and the address/data information to also be
transmitted on slots 1 and 2.
transmitted on slot 12 is the data last written to offset 54h/D4h. Any subsequent write to the
register causes the new data to be sent out on the next frame.
and hence a wake from S3, S4, or S5. Slot 12 remains invalid until the next write to offset 54h/
D4h.
–
11 are reserved and are always stuffed with 0s by the ICH5 AC ’97
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet