FW82801EB Intel, FW82801EB Datasheet - Page 556

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
15.2.9
556
GLOB_STA—Global Status Register
(Audio—D31:F5)
I/O Address:
Default Value:
Lockable:
31:30
23:22
21:20
19:18
Bit
29
28
27
26
25
24
17
16
Reserved.
AC_SDIN2 Resume Interrupt (S2RI) — R/WC. This bit indicates a resume event occurred on
AC_SDIN2. Software clears this bit by writing a 1 to it.
0 = Resume event did not occur.
1 = Resume event occurred.
This bit is not affected by D3
AC_SDIN2 Codec Ready (S2CR)
Bus masters ignore the condition of the codec ready bits, so software must check this bit before
starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Bit Clock Stopped (BCS)
0 = Transition is found on AC_BIT_CLK.
1 = Intel
S/PDIF Interrupt (SPINT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = S/PDIF out channel interrupt status bits have been set.
PCM In 2 Interrupt (P2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM In 2 channel status bits have been set.
Microphone 2 In Interrupt (M2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the Mic in channel interrupts status bits has been set.
Sample Capabilities
audio.
00 = Reserved
01 = 16 and 20-bit Audio supported
10 = Reserved
11 = Reserved
Multichannel Capabilities
channels on PCM Out.
Reserved.
MD3 — R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3
AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3
PCI clocks.
®
ICH5 detected that there has been no transition on AC_BIT_CLK for four consecutive
NABMBAR + 30h
00700000h
No
—
RO. This field indicates the capability to support more greater than 16-bit
—
—
—
HOT
HOT
HOT
—
RO.
RO. This bit indicates that the bit clock is not running.
RO. This field indicates the capability to support more 4 and 6
RO.
to D0 Reset.
to D0 Reset.
to D0 Reset.
—
—
RO. Reflects the state of the codec ready bit on AC_SDIN2.
RO.
Description
Intel
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO, R/W, R/WC
32 bits
Core