FW82801EB Intel, FW82801EB Datasheet - Page 365

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.5.5
9.5.6
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one
Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8.
EOIR—EOI Register
(LPC I/F—D31:F0)
Memory Address
Default Value:
The EOI register is present to provide a mechanism to maintain the level triggered semantics for
level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this
register, and compare it with the vector field for each entry in the I/O Redirection Table. When a
match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which
was prematurely reset will not be lost because if its input remained active when the Remote_IRR
bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are
actually used. Bits 31:8 are ignored by the ICH5.
ID—Identification Register
(LPC I/F—D31:F0)
Index Offset:
Default Value:
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is
derived from its I/O APIC ID. This register is reset to 0 on power up reset.
31:28
27:24
23:16
31:8
14:0
Bit
7:0
Bit
15
Reserved. To provide for future expansion, the processor should always write a value of 0 to
Bits 31:8.
Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this
field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match
is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
Reserved
APIC ID — R/W. Software must program this value before using the APIC.
Reserved
Scratchpad Bit.
Reserved
FEC0_0040h
N/A
00h
00000000h
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Attribute:
Size:
WO
32 bits
R/W
32 bits
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