FW82801EB Intel, FW82801EB Datasheet - Page 303

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

8.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI Command Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The Intel
capability.
SERR# Enable (SERR_EN) — R/W.
0 = Disable
1 = Enable the ICH5 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit
Wait Cycle Control (WCC) — RO. Hardwired to 0
Parity Error Response (PER) — R/W.
0 = The ICH5 ignores parity errors on the hub interface.
1 = The ICH5 is allowed to report parity errors detected on the hub interface.
NOTE: The HP_Unsupported bit (D30:F0:40h bit 20) must be cleared in order for this bit to have
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0 by P2P Bridge specification.
Bus Master Enable (BME) — R/W.
0 = Disable
1 = Enable. Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub
NOTE: This bit does not affect the CF8h and CFCh I/O accesses.
Memory Space Enable (MSE) — R/W. The ICH5 provides this bit as read/writable for software only.
However, the ICH5 ignores the programming of this bit, and runs hub interface memory cycles to
PCI.
I/O Space Enable (IOSE) — R/W. The ICH5 provides this bit as read/writable for software only.
However, the ICH5 ignores the programming of this bit and runs hub interface I/O cycles to PCI that
are not intended for USB, IDE, or AC ’97.
(offset 06h, bit 14) is set.
interface.
any effect.
Cycles that generated from the ICH5’s Device 31 functionality are not blocked by clearing
this bit. (PC/PCI Cascade Mode cycles may be blocked)
04
0001h
–
05h
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Attribute:
Size:
®
ICH5 does not support this
R/W, RO
16 bits
303