FW82801EB Intel, FW82801EB Datasheet - Page 545

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

15.1.23
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCS—Power Management Control and Status Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
14:9
Bit
7:2
1:0
15
8
PME Status (PMES) — R/WC. This bit resides in the resume well. Software clears this bit by writing
a 1 to it.
0 = PME# signal not asserted by AC ‘97 controller.
1 = This bit is set when the AC ’97 controller would normally assert the PME# signal independent of
Reserved — RO.
Power Management Event Enable (PMEE) — R/W.
0 = Disable
1 = Enable. When set, and if corresponding PMES is also set, the AC '97 controller sets the
Reserved—RO.
Power State (PS) — R/W. This field is used both to determine the current power state of the AC’97
controller and to set a new power state. The values are:
00 = D0 state
01 = not supported
10 = not supported
11 = D3
When in the D3
memory spaces are not. Additionally, interrupts are blocked.
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs.
the state of the PME_En bit.
AC97_STS bit in the GPE0_STS register
HOT
54
0000h
No
state
–
HOT
55h
state, the AC ’97 controller’s configuration space is available, but the I/O and
AC ’97 Audio Controller Registers (D31:F5)
Description
Attribute:
Size:
Power Well:
R/W, R/WC
16 bits
Resume
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