FW82801EB Intel, FW82801EB Datasheet - Page 40

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Introduction
40
Chapter 1. Introduction
Chapter 1
Chapter 2. Signal Description
Chapter 2
interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of
all signals.
Chapter 3. Intel
Chapter 3
suspend state, and their logic level before and after reset.
Chapter 4. Intel
Chapter 4
Chapter 5. Functional Description
Chapter 5
functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function.
This manual abbreviates buses as B0 and B1, devices as D8, D29, D30 and D31 and functions as
F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 5 is abbreviated as D31:F5,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used,
and can be considered to be Bus 0. Note that the ICH5’s external PCI bus is typically Bus 1, but
may be assigned a different number depending upon system configuration.
Chapter 6. Register and Memory Mappings
Chapter 6
ranges decoded by the ICH5.
Chapter 7. LAN Controller Registers
Chapter 7
controller. The integrated LAN controller resides on the ICH5’s external PCI bus (typically Bus 1)
at Device 8, Function 0 (B1:D8:F0).
Chapter 8. Hub Interface to PCI Bridge Registers
Chapter 8
bridge. This bridge resides at Device 30, Function 0 (D30:F0).
Chapter 9. LPC Bridge Registers
Chapter 9
resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units
within the ICH5 including DMA, Timers, Interrupts, Processor Interface, GPIO, Power
Management, System Management and RTC.
Chapter 10. IDE Controller Registers
Chapter 10
controller resides at Device 31, Function 1 (D31:F1).
Chapter 11. SATA Controller Registers
Chapter 11
controller resides at Device 31, Function 2 (D31:F2).
Chapter 12. UHCI Controller Registers
Chapter 12
controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3 (D29:F0/F1/F2/F3).
introduces the ICH5 and provides information on manual organization.
provides a detailed description of each ICH5 signal. Signals are arranged according to
provides a complete list of signals, their associated power well, their logic level in each
provides a list of each clock domain associated with the ICH5 in an ICH5-based system.
provides a detailed description of the functions in the ICH5. All PCI buses, devices and
provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory
provides a detailed description of all registers that reside in the ICH5’s integrated LAN
provides a detailed description of all registers that reside in the Hub Interface to PCI
provides a detailed description of all registers that reside in the LPC bridge. This bridge
provides a detailed description of all registers that reside in the SATA controller. This
provides a detailed description of all registers that reside in the IDE controller. This
provides a detailed description of all registers that reside in the four UHCI host
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ICH5 Power Planes and Pin States
ICH5 and System Clock Domains
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet