FW82801EB Intel, FW82801EB Datasheet - Page 274

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Register and Memory Mapping
6.4.1
274
Table 133. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
Note: The top-block swap mode may be forced by an external strapping option (See
Note: Top-block swap mode only affects accesses to the flash BIOS space, not feature space.
Note: The top-block swap mode has no effect on accesses below FFFE_0000h.
NOTES:
Boot-Block Update Scheme
The ICH5 supports a “top-block swap” mode that has the ICH5 swap the top block in the flash
BIOS (the boot block) with another location. This allows for safe update of the Boot Block (even if
a power failure occurs). When the “TOP_SWAP” Enable bit is set, the ICH5 will invert A16 for
cycles targeting flash BIOS space. When this bit is 0, the ICH5 will not invert A16. This bit is
automatically set to 0 by RTCRST#, but not by PCIRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block, and the block
immediately below the top block is reserved for doing boot-block updates.
The algorithm is:
If a power failure occurs at any point after step 3, the system will be able to boot from the copy of
the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is
backed in the RTC well.
When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by
software. A re-boot with the strap removed will be required to exit a forced top-block swap mode.
1. These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on PCI.
2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI, High-Precision Event Timers,
Memory Range
1 KB anywhere in 4 GB
range
FED0 X000–FED0 X3FF
All other
1. Software copies the top block to the block immediately below the top
2. Software checks that the copied block is correct. This could be done by performing a
3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the flash BIOS.
4. Software erases the top block
5. Software writes the new top block
6. Software checks the new top block
7. Software clears the TOP_SWAP bit
8. Software sets the Top_Swap Lock-Down bit
and IDE Expansion. If attempted, the lock is not honored, which means potential deadlock conditions may
occur.
checksum calculation.
processor access to FFFF_0000h through FFFF_FFFFh will be directed to FFFE_0000h
through FFFE_FFFFh in the flash BIOS, and processor accesses to FFFE_0000h through
FFFE_FFFF will be directed to FFFF_0000h through FFFF_FFFFh.
High-Precision Event
Controller
USB EHCI
Timers
Target
PCI
1,2
1,2
Intel
Enable via standard PCI mechanism (Device 29,
Function 7)
BIOS determines the “fixed” location which is one of
four, 1-KB ranges where X (in the first column) is 0h,
1h, 2h, or 3h.
None
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Dependency/Comments
Section
2.21.1).