FW82801EB Intel, FW82801EB Datasheet - Page 525

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

14.2.3
14.2.4
14.2.5
14.2.6
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
HST_CMD—Host Command Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
XMIT_SLVA—Transmit Slave Address Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
This register is transmitted by the host controller in the slave address field of the SMBus protocol.
HST_D0—Host Data 0 Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
HST_D1—Host Data 1 Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Bit
7:1
Bit
7:0
Bit
7:0
Bit
7:0
0
Address — R/W. This field provides a 7-bit address of the targeted slave.
RW — R/W. Direction of the host transfer.
0 = Write
1 = Read
Data0/Count — R/W. This field contains the eight bit data sent in the DATA0 field of the SMBus
protocol. For block write commands, this register reflects the number of bytes to transfer. This
register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a
count above 32 will result in unpredictable behavior. The host controller does not check or log illegal
block counts.
Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol during the
execution of any command.
This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol
during the execution of any command.
03h
00h
04h
00h
05h
00h
06h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
R/W
8 bits
R/W
8 bits
R/W
8 bits
R/W
8 bits
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