FW82801EB Intel, FW82801EB Datasheet - Page 394

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.7
394
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this
register should be cleared to 0 based on a Power Button Override or processor Thermal Trip event.
The resume well bits are all cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
31:16
Bit
15
14
13
12
Bit
2
1
0
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a
SCI, and/or wake event. These bits are cleared by RSMRST#.
Reserved
USB4_EN — R/W.
0 = Disable
1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS bit is set
PME_B0_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
0 = Disable
1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS bit is set
Reserved
Thermal Interrupt Override Status ( THRMOR_STS) — R/WC. Software clears this bit by writing
a 1 to it.
0 = Thermal over-ride condition did not occur and start throttling the processor’s clock at the
1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling
Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = THRM# signal not driven active as defined by the THRM_POL bit
1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL
anytime USB UHCI controller #4 signals a wake event. Break events are handled via the
USB interrupt.
SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from S5 (if entered via
SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit defaults to
0.
anytime USB UHCI controller #3 signals a wake event. Break events are handled via the
USB interrupt.
THRM_DTY ratio
the processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake
event.
bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also
generate a power management event (SCI or SMI#).
PMBASE + 2Ch
( ACPI GPE0_BLK + 4 )
00000000h
No
Bits 0
Bits 8
–
–
7, 12, 16
11, 13
–
15 RTC
–
31 Resume,
Intel
Description
Description
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32-bit
ACPI