FW82801EB Intel, FW82801EB Datasheet - Page 655

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 206. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
B1:D8:F0)” on page 281 CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE — CSR I/O-Mapped Base
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
EEPROM Control Register
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
General Purpose Event 0
Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status Register
Alternate GPI SMI Enable
Alternate GPI SMI Status
Section 7.1.11, “CSR_MEM_BASE — CSR Memory-Mapped Base Address Register (LAN Controller—
®
Register Name
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.
LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in
ICH5 Variable I/O Registers (Sheet 1 of 6)
Address Register (LAN Controller—B1:D8:F0)” on page 281
Power Management I/O Registers at PMBASE+Offset
OBh – 08h
0Fh – 0Eh
1Ah – 19h
01h – 00h
03h – 02h
07h – 04h
13h – 10h
17h – 14h
10h – 13h
2C – 2Fh
3A – 3Bh
08 – 0Bh
28 – 2Bh
00 – 01h
02 – 03h
04 – 07h
30 – 31h
34 – 35h
38 – 39h
Offset
1Bh
1Ch
1Dh
18h
Section 7.2.1, “SCB_STA—System Control Block Status Word
Register (LAN Controller—B1:D8:F0)” on page 288
Section 7.2.2, “SCB_CMD—System Control Block Command
Word Register (LAN Controller—B1:D8:F0)” on page 289
Section 7.2.3, “SCB_GENPNT—System Control Block General
Pointer Register (LAN Controller—B1:D8:F0)” on page 291
Section 7.2.4, “PORT—PORT Interface Register (LAN
Controller—B1:D8:F0)” on page 291
Section 7.2.5, “EEPROM_CNTL—EEPROM Control Register
(LAN Controller—B1:D8:F0)” on page 292
Section 7.2.6, “MDI_CNTL—Management Data Interface (MDI)
Control Register (LAN Controller—B1:D8:F0)” on page 293
Section 7.2.7, “REC_DMA_BC—Receive DMA Byte Count
Register (LAN Controller—B1:D8:F0)” on page 293
Section 7.2.8, “EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0)” on page 294
Section 7.2.9, “FLOW_CNTL—Flow Control Register (LAN
Controller—B1:D8:F0)” on page 295
Section 7.2.10, “PMDR—Power Management Driver Register
(LAN Controller—B1:D8:F0)” on page 296
Section 7.2.11, “GENCNTL—General Control Register (LAN
Controller—B1:D8:F0)” on page 297
Section 7.2.12, “GENSTA—General Status Register (LAN
Controller—B1:D8:F0)” on page 297
Section 9.10.1, “PM1_STS—Power Management 1 Status
Register” on page 386
Section 9.10.2, “PM1_EN—Power Management 1 Enable
Register” on page 388
Section 9.10.3, “PM1_CNT—Power Management 1 Control” on
page 389
Section 9.10.4, “PM1_TMR—Power Management 1 Timer
Register” on page 390
Section 9.10.5, “PROC_CNT—Processor Control Register” on
page 390
Section 9.10.6, “GPE0_STS—General Purpose Event 0 Status
Register” on page 392
Section 9.10.7, “GPE0_EN—General Purpose Event 0 Enables
Register” on page 394
Section 9.10.8, “SMI_EN—SMI Control and Enable Register” on
page 396
Section 9.10.9, “SMI_STS—SMI Status Register” on page 398
Section 9.10.10, “ALT_GP_SMI_EN—Alternate GPI SMI Enable
Register” on page 400
Section 9.10.11, “ALT_GP_SMI_STS—Alternate GPI SMI Status
Register” on page 400
Datasheet Section and Location
Register Index
655