FW82801EB Intel, FW82801EB Datasheet - Page 144

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.12.2.2
5.12.3
144
Table 57. Frequency Strap Behavior Based on Exit State
Power Management
Attempting clock control with more than one processor is not feasible, because the Host controller
does not provide any indication as to which processor is executing a particular Stop-Grant cycle.
Without this information, there is no way for the ICH5 to know when it is safe to deassert
STPCLK#.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected
to both processors. The BIOS must indicate that the ICH5 only supports the C1 state for dual-
processor designs. However, the THRM# signal can be used for overheat conditions to activate
thermal throttling.
When entering S1, the ICH5 asserts STPCLK# to both processors. To meet the processor
specifications, the CPUSLP# signal will have to be delayed until the second Stop-Grant cycle
occurs. To ensure this, the ICH5 waits a minimum or 60 PCI clocks after receipt of the first Stop-
Grant cycle before asserting CPUSLP# (if the SLP_EN bit is set to 1).
Both processors must immediately respond to the STPCLK# assertion with stop grant
acknowledge cycles before the ICH5 asserts CPUSLP# in order to meet the processor setup time
for CPUSLP#. Meeting the processor setup time for CPUSLP# is not an issue if both processors are
idle when the system is entering S1. If you cannot guarantee that both processors will be idle, do
not enable the SLP_EN bit. Note that setting SLP_EN to 1 is not required to support S1 in a dual-
processor configuration.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state; thus,
STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose
power. Upon exit from those states, the processors will have their power restored.
Speed Strapping for Processor
The ICH5 directly sets the speed straps for the processor, saving the external logic that has been
needed with prior PCIsets. Refer to processor specification for speed strapping definition.
The ICH5 performs the following to set the speed straps for the processor:
S3, S4, S5,
1. While PCIRST# is active, the ICH5 drives A20M#, IGNNE#, NMI, and INTR high.
2. As soon as PWROK goes active, the ICH5 reads the FREQ_STRAP field contents.
3. The next step depends on the power state being exited as described in
Exiting
State
or G3
S1
There is no processor reset, so no frequency strap logic is used.
Based on PWROK going active, the Intel
the FREQ_STRAP field (D31:F0,Offset D4), the ICH5 drives the intended core frequency values
on A20M#, IGNNE#, NMI, and INTR.
Intel
®
Intel
ICH5 deasserts PCIRST#, and based on the value of
®
®
82801EB ICH5 / 82801ER ICH5R Datasheet
ICH5
Table
57.