FW82801EB Intel, FW82801EB Datasheet - Page 547

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 169. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
NOTE:
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC ’97
controller. Accesses to these registers do not cause the cycle to be forwarded over the AC-link to
the codec. S/W could access these registers as bytes, word, DWord or qWord quantities, but reads
must not cross DWord boundaries.
In the case of the split codec implementation accesses to the different codecs are differentiated by
the controller by using address offsets 00h
the secondary codec and address offsets 100h
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the
same global registers in the audio and modem I/O space. Therefore a read/write to these registers in
either audio or modem I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC ’97 controller. The six channels,
PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their own set of Bus
Mastering registers. The following register descriptions apply to all six channels. The register
definition section titles use a generic “x_” in front of the register to indicate that the register applies
to all six channels. The naming prefix convention used in
I/O address is as follows:
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
1. Software should not try to access reserved registers
2. Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of configuration
3. The tertiary offset is only available through the memory space defined by the MMBAR register.
Primary Offset
(Codec ID =00)
register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration register 40h.
®
7Ch
5Ah
7Eh
ICH5 Audio Mixer Register Configuration (Sheet 2 of 2)
Secondary Offset
(Codec ID =01)
DAh
FCh
FEh
–
7Fh for the primary codec, address offsets 80h
Tertiary Offset
(Codec ID =10
–
17Fh for the tertiary codec.
AC ’97 Audio Controller Registers (D31:F5)
17Ch
15Ah
17Eh
Table 170
Vendor Reserved
Vendor ID1
Vendor ID2
NAMBAR Exposed Registers
and in the register description
(D31:F5)
–
FFh for
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