FW82801EB Intel, FW82801EB Datasheet - Page 188

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.17.4.2.2
5.17.4.3
5.17.5
5.18
188
Table 79. SATA MSI vs. PCI IRQ Actions
SMI Trapping (APM)
Device D1, D3 States
These states are entered after some period of time when software has determined that no
commands will be sent to this device for some time. The mechanism for putting a device in these
states does not involve any work on the host controller, other then sending commands over the
interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY
IMMEDIATE” command.
Offset 48h, bits 3:0 in the power management I/O space (see
generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges
(1F0
these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not
be forwarded to the SATA controller, and for an SMI# to be generated. If an access to the
Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the
register is updated, an SMI# is generated, and the device activity status bits
updated indicating that a trap occurred.
To block accesses to the native IDE ranges, software must use the generic power management
control registers described in
SATA Interrupts
Table 79
four possible interrupt bits in I/O space, which are: PSTS.PRDIS (offset 02h, bit 7), PSTS.I
(offset 02h, bit 2), SSTS.PRDIS (offset 0Ah, bit 7), and SSTS.I (offset 0Ah, bit 2).
High-Precision Event Timers
This function provides a set of timers that can be used by the operating system. The timers are
defined such that in the future, the operating system may be able to assign specific timers to used
directly by specific applications. Each timer can be configured to cause a separate interrupt.
ICH5 provides three timers. The three timers are implemented as a single counter each with its own
comparator and value register. This counter increases monotonically. Each individual timer can
generate an interrupt when the value in its value register matches the value in the main counter.
All bits are 0
One or more bits set to 1
One or more bits set to 1, new bit gets set to 1
One or more bits set to 1, software clears some (but not all) bits
One or more bits set to 1, software clears all bits
Software clears one or more bits, and one or more bits is set
simultaneously
–
1F7h, 3F6h, 170
summarizes interrupt behavior for MSI and wire-modes. In the table “bits” refers to the
Interrupt Register
–
177h, and 376h). If the SATA controller is in legacy mode and is using
Section
9.8.9.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Wire-Mode Action
Section
Wire Inactive
Wire Inactive
Wire Active
Wire Active
Wire Active
Wire Active
9.10.14) contain control for
(Section
Send Message
Send Message
Send Message
Send Message
MSI Action
No Action
No Action
9.10.13) are