FW82801EB Intel, FW82801EB Datasheet - Page 217

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.20.3.1.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Prefetching is limited to the current and next microframes only.
Note: Once the PDE checks the length of a periodic packet against the remaining time in the microframe
Read Policies for Periodic DMA
The Periodic DMA engine performs reads for the following structures.
The EHC Periodic DMA Engine (PDE) does not generate accesses to main memory unless all three
of the following conditions are met.
(late-start check) and decides that there is not enough time to run it on the wire, then the EHC
switches over to run asynchronous traffic.
Periodic Frame List entry
iTD
siTD
qTD
Queue Head
Out Data
Frame Span Transversal
Node
•
•
•
Memory Structure
The HCHalted bit is 0 (memory space, offset 24h, bit 12). Software clears this bit indirectly by
setting the RUN/STOP bit to 1.
The Periodic Schedule Status bit is 1 (memory space, offset 24h, bit 14). Software sets this bit
indirectly by setting the Periodic Schedule Enable Bit to 1.
The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2).
Size (DWords)
Up to 257
23
13
17
1
9
2
The EHC reads the entry for each microframe. The frame list is
not internally cached across microframes.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
The Intel
aligned read requests based on the setting of the Read Request
Max Length field.
®
ICH5 breaks large read requests down into smaller
Comments
Functional Description
217