FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 332
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FW82801EB S L73Z
Manufacturer Part Number
FW82801EB S L73Z
Description
Manufacturer
Intel
Datasheet
1.FW82801EB_S_L73Z.pdf
(671 pages)
Specifications of FW82801EB S L73Z
Lead Free Status / RoHS Status
Not Compliant
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LPC Interface Bridge Registers (D31:F0)
9.1.23
332
GEN_STA—General Status Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
Bit
7:3
2
1
0
Reserved
Safe Mode (SAFE_MODE) — RO.
0 = Intel
1 = ICH5 sampled AC_SDOUT high on the rising edge of PWROK. ICH5 will force
No Reboot (NO_REBOOT) — R/W (special).
0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO timeout). This bit cannot be set to
1 = ICH5 disables the TCO Timer system reboot feature. This bit is set either by hardware when
Reserved
FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).
0 by software if the strap is set to No Reboot.
SPKR is sampled high on the rising edge of PWROK, or by software writing a 1 to the bit.
®
ICH5 sampled AC_SDOUT low on the rising edge of PWROK.
D4h
0Xh
No
Intel
Description
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W (special), RO
8 bit
Core
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