FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 647
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FW82801EB S L73Z
Manufacturer Part Number
FW82801EB S L73Z
Description
Manufacturer
Intel
Datasheet
1.FW82801EB_S_L73Z.pdf
(671 pages)
Specifications of FW82801EB S L73Z
Lead Free Status / RoHS Status
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Intel
®
Table 204. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Interrupt Line
Interrupt Pin
Power Management
Capability ID
Next Item Pointer
Power Management
Capabilities
Power Management
Control and Status
Debug Port Capability ID
Next Item Pointer #2
Debug Port Base Offset
USB Release Number
Frame Length Adjustment
Power Wake Capabilities
USB 2.0 Legacy Support
Extended Capability
USB 2.0 Legacy Support
Control and Status
Intel Specific USB 2.0 SMI
Access Control
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
®
Register Name
ICH5 PCI Configuration Registers (Sheet 9 of 11)
5A – 5Bh
6C – 6Fh
68 – 6Bh
52 – 53h
54 – 55h
62 – 63h
70 – 73h
00 – 01h
02 – 03h
04 – 05h
06 – 07h
Offset
3Ch
3Dh
0Ah
50h
51h
58h
59h
60h
61h
80h
08h
09h
SMBus Controller (D31:F3)
Section 13.1.14, “INT_LN—Interrupt Line Register (USB EHCI—
D29:F7)” on page 485
Section 13.1.15, “INT_PN—Interrupt Pin Register (USB EHCI—
D29:F7)” on page 485
Section 13.1.16, “PWR_CAPID—PCI Power Management
Capability ID Register (USB EHCI—D29:F7)” on page 486
Section 13.1.17, “NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F7)” on page 486
Section 13.1.18, “PWR_CAP—Power Management Capabilities
Register (USB EHCI—D29:F7)” on page 487
Section 13.1.19, “PWR_CNTL_STS—Power Management
Control/Status Register (USB EHCI—D29:F7)” on page 488
Section 13.1.20, “DEBUG_CAPID—Debug Port Capability ID
Register (USB EHCI—D29:F7)” on page 488
Section 13.1.21, “NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F7)” on page 489
Section 13.1.22, “DEBUG_BASE—Debug Port Base Offset
Register (USB EHCI—D29:F7)” on page 489
Section 13.1.23, “USB_RELNUM—USB Release Number
Register (USB EHCI—D29:F7)” on page 489
Section 13.1.24, “FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F7)” on page 490
Section 13.1.25, “PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F7)” on page 491
Section 13.1.26, “LEG_EXT_CAP—USB EHCI Legacy Support
Extended Capability Register (USB EHCI—D29:F7)” on
page 491
Section 13.1.27, “LEG_EXT_CS—USB EHCI Legacy Support
Extended Control / Status Register (USB EHCI—D29:F7)” on
page 492
Section 13.1.28, “SPECIAL_SMI—Intel Specific USB 2.0 SMI
Register (USB EHCI—D29:F7)” on page 493
Section 13.1.28, “SPECIAL_SMI—Intel Specific USB 2.0 SMI
Register (USB EHCI—D29:F7)” on page 493
Section 14.1.1, “VID—Vendor Identification Register (SMBUS—
D31:F3)” on page 515
Section 14.1.2, “DID—Device Identification Register (SMBUS—
D31:F3)” on page 516
Section 14.1.3, “PCICMD—PCI Command Register (SMBUS—
D31:F3)” on page 516
Section 14.1.4, “PCISTS—PCI Status Register (SMBUS—
D31:F3)” on page 517
Section 14.1.5, “RID—Revision Identification Register
(SMBUS—D31:F3)” on page 517
Section 14.1.7, “BCC—Base Class Code Register (SMBUS—
D31:F3)” on page 518
Datasheet Section and Location
Register Index
647
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