FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 425

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

10.1.20
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1)
Address Offset:
Default Value:
Bit
7:6
Bit
4
3
2
1
0
Secondary Drive 1 IORDY Sample Point (SISP1) — R/W. This field determines the number of PCI
clocks between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive
1 data port and bit 14 of the IDE timing register for secondary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Drive 1 Fast Timing Bank (TIME1) — R/W.
0 = Accesses to the data port will use compatible timings for this drive.
1 = When this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY
Drive 0 DMA Timing Enable (DTE0) — R/W.
0 = Disable
1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
Drive 0 Prefetch/Posting Enable (PPE0) — R/W.
0 = Disable prefetch and posting to the IDE data port for this drive.
1 = Enable prefetch and posting to the IDE data port for this drive.
Drive 0 IORDY Sample Point Enable (IE0) — R/W.
0 = Disable IORDY sampling is disabled for this drive.
1 = Enable IORDY sampling for this drive.
Drive 0 Fast Timing Bank (TIME0) — R/W.
0 = Accesses to the data port will use compatible timings for this drive.
1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the
sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to
the data port will use the IORDY sample point and recover time specified in the slave IDE
timing register.
port will run in compatible timing.
recovery time
44h
00h
Description
Description
Attribute:
Size:
IDE Controller Registers (D31:F1)
R/W
8 bits
425