FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 385
FW82801EB S L73Z
Manufacturer Part Number
FW82801EB S L73Z
Description
Manufacturer
Intel
Datasheet
1.FW82801EB_S_L73Z.pdf
(671 pages)
Specifications of FW82801EB S L73Z
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Intel
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Table 151. ACPI and Legacy I/O Register Map
82801EB ICH5 / 82801ER ICH5R Datasheet
PMBASE
Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.
10h–13h
14h–16h
42h–43h
51h–5Fh
60h–7Fh
+ Offset
0C–0Fh
2C–2Fh
3A–3Bh
3C–3Fh
08–0Bh
28–2Bh
00–01h
02–03h
04–07h
17–1Fh
30–33h
34–37h
38–39h
20h
40h
44h
48h
50h
Power Management I/O Registers
Table 151
These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be
moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the
Advanced Configuration and Power Interface, Version 2.0b, and use the same bit names.
ALT_GP_SMI_STS Alternate GPI SMI Status
ALT_GP_SMI_EN
DEVTRAP_EN
DEVACT_STS
PROC_CNT
GPE0_STS
Mnemonic
PM1_CNT
PM1_TMR
MON_SMI
PM1_STS
GPE0_EN
SMI_STS
PM1_EN
SMI_EN
—
—
—
—
—
—
—
—
shows the registers associated with ACPI and Legacy power management support.
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Reserved
Processor Control
Reserved
Reserved
Reserved
General Purpose Event 0 Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status
Alternate GPI SMI Enable
Reserved
Monitor SMI Status
Reserved
Device Activity Status
Device Trap Enable
Reserved
Reserved
Reserved for TCO
Register Name
LPC Interface Bridge Registers (D31:F0)
PM1a_EVT_BLK
PM1a_EVT_BLK+2
PM1a_CNT_BLK
PMTMR_BLK
—
P_BLK
—
—
—
GPE0_BLK
GPE0_BLK+4
—
—
—
—
ACPI Pointer
00000000h
00000000h
00000000h
00000000h
00000000h
Default
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
—
—
—
—
—
—
—
—
R/W, RO, WO
R/W (special)
R/W, R/WC
R/W, R/WC
R/WC, RO
R/W, WO,
R/W, WO
R/WC
R/WC
R/WC
Type
R/W
R/W
R/W
R/W
RO
—
—
—
—
—
—
—
—
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