NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 272
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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7.1.11
7.1.12
7.1.13
272
V1STS—Virtual Channel 1 Resource Status Register
Offset Address: 0026–0027h
Default Value:
PAT—Port Arbitration Table
Offset Address: 0030–006Fh
Default Value:
This is a 64-byte register that contains the arbitration table to be loaded into the port
arbitration table. Every 4-bits contains an entry for one of the downstream PCI-Express
ports or a 0h to indicate idle. The ports are mapped as follows:
This table is copied to an internal structure used during port arbitration when
V1CTL.PAS is set to 04h, and V1CTL.LAT is set to 1.
CIR1—Chipset Initialization Register 1
Offset Address: 0088–008Bh
Default Value:
• Port 1: Value used is 1h.
• Port 2: Value used is 2h.
• Port 3: Value used is 3h
• Port 4: Value used is 4h
• Port 5: Value used is 5h
• Port 6: Value used is 6h
• Intel
15:02
31:21
19:16
14:13
11:0
Bit
Bit
20
15
12
1
0
®
Reserved
VC Negotiation Pending (NP) — RO. When set, indicates the virtual channel is still
being negotiated with ingress ports.
Port Arbitration Tables Status (ATS) — RO. Indicates the coherency status of the
port arbitration table. This bit is set when LAT (offset 000Ch:bit 0) is written with
value 1 and PAS (offset 0014h:bits19:17) has value of 4h. This bit is cleared after the
table has been updated.
Reserved
CIR1 Field 3 — R/WO. BIOS must set this bit.
Reserved
CIR1 Field 2 — R/WO. BIOS must set this bit.
Reserved
CIR1 Field 1— R/WO. BIOS must set this bit.
Reserved
High Definition Audio: Value used is Fh
0000h
00000000h
Description
Description
Attribute:
Size:
Size:
Attribute:
Size:
Attribute:
Chipset Configuration Registers
RO
16-bit
64-Byte
R/WO, RO
32-bit
Intel
®
ICH8 Family Datasheet
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