NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 728
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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18.1.47
18.1.48
728
RPDCGEN—Root Port Dynamic Clock Gating Enable
(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)
Address Offset: E1h
Default Value:
IPWS—Intel
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: E2h–E3h
Default Value:
14:0
Bits
7:4
Bit
15
3
2
1
0
Reserved. RO
Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — RW.
1 = Enables dynamic clock gating on the root port shared resource link clock domain.
0 = Disables dynamic clock gating of the shared resource link clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5-6.
Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — RW.
1 = Enables dynamic clock gating on the root port shared resource backbone clock
domain.
0 = Disables dynamic clock gating of the shared resource backbone clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5-6.
Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — RW.
1 = Enables dynamic clock gating on the root port link clock domain.
0 = Disables dynamic clock gating of the root port link clock domain.
Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — RW.
1 = Enables dynamic clock gating on the root port backbone clock domain.
0 = Disables dynamic clock gating of the root port backbone clock domain.
Intel PRO/Wireless 3945ABG Status (IPWSTAT) — RO. This bit is set if the link
has trained to L0 in Intel PRO/Wireless 3945ABG mode.
Reserved
00h
0007h
®
PRO/Wireless 3945ABG Status
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
R/W
8-bits
RO
16 bits
Intel
®
ICH8 Family Datasheet
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