NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 639
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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SMBus Controller Registers (D31:F3)
16.2.14
Note:
16.2.15
Note:
Intel
®
ICH8 Family Datasheet
SMBUS_PIN_CTL—SMBus Pin Control Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 0Fh
Default Value:
This register is in the resume well and is reset by RSMRST#.
SLV_STS—Slave Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 10h
Default Value:
This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
7:3
7:1
Bit
Bit
2
1
0
0
Reserved
SMBCLK_CTL — R/W.
0 = ICH8 drives the SMBCLK pin low, independent of what the other SMB logic would
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of
SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent
on an external signal level. This pin returns the value on the SMBDATA pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMBCLK pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
Reserved
HOST_NOTIFY_STS — R/WC. The ICH8 sets this bit to a 1 when it has completely
received a successful Host Notify Command on the SMLink pins. Software reads this bit
to determine that the source of the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading any information needed from
the Notify address and data registers by writing a 1 to this bit. Note that the ICH8 will
allow the Notify Address and Data registers to be over-written once this bit has been
cleared. When this bit is 1, the ICH8 will NACK the first byte (host address) of any new
“Host Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
otherwise indicate for the SMBCLK pin. (Default)
the pin.
See below
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, RO
8 bits
R/WC
8 bits
639
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