NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 649
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Compliant
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Intel
17.1.11
17.1.12
17.1.13
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
HEADTYP—Header Type Register
(Intel
Address Offset: 0Eh
Default Value:
HDBARL—Intel
Address Register (Intel
Address Offset: 10h–13h
Default Value:
HDBARU—Intel
Address Register (Intel
Controller—D27:F0)
Address Offset: 14h–17h
Default Value:
31:14
13:4
31:0
7:0
2:1
Bit
Bit
Bit
3
0
Header Type — RO. Hardwired to 00.
Lower Base Address (LBA) — R/W. Base address for the Intel
controller’s memory-mapped configuration registers. A 16 KB size are requested by
hardwiring bits 13:4 to 0s.
RO. Hardwired to 0’s
Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable
Address Range (ADDRNG) — RO. Hardwired to 10b indicating that this BAR can be
located anywhere in 64-bit address space.
Space Type (SPTYP) — RO. Hardwired to 0 indicating this BAR is located in memory
space.
Upper Base Address (UBA) — R/W. This field contains the upper 32 bits of the Base
address for the Intel
registers.
®
High Definition Audio Controller—D27:F0)
00h
00000004h
00000000h
®
®
High Definition Audio Lower Base
High Definition Audio Upper Base
®
High Definition Audio controller’s memory-mapped configuration
®
®
High Definition Audio—D27:F0)
High Definition Audio
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W, RO
32 bits
R/W
32 bits
®
High Definition Audio
649
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