NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 739
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 739 of 890
- Download datasheet (7Mb)
PCI Express* Configuration Registers
18.1.66
18.1.67
Intel
®
ICH8 Family Datasheet
ULBA — Upstream Link Base Address Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 198h
Default Value:
PEETM — PCI Express* Extended Test Mode Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 318h
Default Value:
63:32
31:0
7:3
1:0
Bit
Bit
2
Base Address Upper (BAU) — RO. The RCRB of the Intel
Base Address Lower (BAL) — RO. This field matches the RCBA register
(D31:F0:Offset F0h) value in the LPC bridge.
Reserved
Scrambler Bypass Mode (BAU) — R/W.
0 = Normal operation. Scrambler and descrambler are used.
1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in
NOTE: This functionality intended for debug/testing only.
NOTE: If bypassing scrambler with ICH8 root port 1 in x4 configuration, each ICH8 root
Reserved
the receive direction.
port must have this bit set.
See Description
See Description
–
19Fh
§ §§
Description
Description
Attribute:
Size:
Attribute:
Size:
®
RO
64 bits
RO
8 bits
ICH8 is in 32-bit space.
739
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