NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 461
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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IDE Controller Registers (D31:F1) (Mobile Only)
11.1.26
11.1.27
Intel
®
ICH8 Family Datasheet
ATC—APM Trapping Control Register (IDE—D31:F1)
Address Offset:
Default Value:
ATS—APM Trapping Status Register (IDE—D31:F1)
Address Offset:
Default Value:
7:2
7:2
Bit
Bit
1
0
1
0
Reserved
Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/O
accesses to 1F0h-1F7h and 3F6h. The active device must be the slave device for the
trap and/or SMI# to occur.
Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy I/O
accesses to 1F0h-1F7h and 3F6h. The active device must be master device for the trap
and/or SMI# to occur.
Reserved
Slave Trap Status (PSTS) — R/WC. Indicates that a trap occurred to the slave device
Master Trap Status (PMTS) — R/WC. Indicates that a trap occurred to the master
device
C0h
00h
C4h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/WC
8 bits
461
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