NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 648
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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17.1.6
17.1.7
17.1.8
17.1.9
17.1.10
648
PI—Programming Interface Register
(Intel
Offset:
Default Value:
SCC—Sub Class Code Register
(Intel
Address Offset: 0Ah
Default Value:
BCC—Base Class Code Register
(Intel
Address Offset: 0Bh
Default Value:
CLS—Cache Line Size Register
(Intel
Address Offset: 0Ch
Default Value:
LT—Latency Timer Register
(Intel
Address Offset: 0Dh
Default Value:
7:0
7:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Bit
Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to
the ICH8
Latency Timer — RO. Hardwired to 00
®
Programming Interface — RO.
®
Sub Class Code (SCC) — RO.
03h = Audio Device
®
Base Class Code (BCC) — RO.
04h = Multimedia device
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
09h
00h
03h
04h
00h
00h
Intel
®
Description
Description
Description
Description
Description
High Definition Audio Controller Registers (D27:F0)
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
RO
8 bits
R/W
8 bits
RO
8 bits
Intel
®
ICH8 Family Datasheet
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