NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 334
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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9.1.20
334
LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address: 82h
Default Value:
15:14
7:4
Bit
13
12
11
10
9
8
3
2
1
0
Reserved
CNF2_LPC_EN — R/W. Microcontroller Enable # 2.
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This
CNF1_LPC_EN — R/W. Super I/O Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This
MC_LPC_EN — R/W. Microcontroller Enable # 1.
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This
KBC_LPC_EN — R/W. Keyboard Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This
GAMEH_LPC_EN — R/W. High Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This
GAMEL_LPC_EN — R/W. Low Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This
Reserved
FDD_LPC_EN — R/W. Floppy Drive Enable
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected
LPT_LPC_EN — R/W. Parallel Port Enable
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in
COMB_LPC_EN — R/W. Com Port B Enable
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is
COMA_LPC_EN — R/W. Com Port A Enable
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is
range is used for a microcontroller.
range is used for Super I/O devices.
range is used for a microcontroller.
range is used for a microcontroller.
range is used for a gameport.
range is used for a gameport.
in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).
the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
0000h
–
83h
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
16 bit
Core
Intel
®
ICH8 Family Datasheet
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