NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 631
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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SMBus Controller Registers (D31:F3)
16.2
Table 138.
Intel
®
ICH8 Family Datasheet
SMBus I/O and Memory Mapped I/O Registers
SMBus I/O and Memory Mapped I/O Register Address Map
SMB_BASE
+ Offset
0Ah–0Bh
0Dh
00h
02h
03h
04h
05h
06h
07h
08h
09h
0Ch
0Eh
10h
11h
14h
16h
17h
0Fh
HOST_BLOCK_DB
SMLINK_PIN_CTL
SMBUS_PIN_CTL
NOTIFY_DADDR
NOTIFY_DHIGH
NOTIFY_DLOW
Mnemonic
XMIT_SLVA
RCV_SLVA
SLV_DATA
HST_CMD
HST_CNT
SLV_CMD
HST_STS
AUX_STS
AUX_CTL
SLV_STS
HST_D0
HST_D1
PEC
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Packet Error Check
Receive Slave Address
Receive Slave Data
Auxiliary Status
Auxiliary Control
SMLink Pin Control (TCO
Compatible Mode)
SMBus Pin Control
Slave Status
Slave Command
Notify Device Address
Notify Data Low Byte
Notify Data High Byte
Register Name
See register
See register
description
description
Default
0000h
00h
00h
00h
00h
44h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/WC (special)
R/WC, RO,
R/WC, RO
R/W, WO
R/W, RO
R/W, RO
R/WC
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
631
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