NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 737
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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PCI Express* Configuration Registers
18.1.62
18.1.63
Intel
®
ICH8 Family Datasheet
RES — Root Error Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 170h
Default Value:
RCTCL — Root Complex Topology Capability List Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 180
Default Value:
31:20
19:16
15:0
31:27
26:4
Bit
Bit
3
2
1
0
Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error
interrupt allocated.
Reserved
Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel
one error will be captured.
ERR_FATAL/NONFATAL Received (ENR) — R/WC.
0 = No error message received.
1 = Either a fatal or a non-fatal error message is received.
Multiple ERR_COR Received (MCR) — RO. For ICH8, only one error will be captured.
ERR_COR Received (CR) — R/WC.
0 = No error message received.
1 = A correctable error message is received.
Next Capability (NEXT) — RO. Indicates the next item in the list, in this case, end of
list.
Capability Version (CV) — RO. Indicates the version of the capability structure.
Capability ID (CID) — RO. Indicates this is a root complex topology capability.
00000000h
00010005h
–
183h
–
173h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/WC, RO
32 bits
RO
32 bits
®
ICH8, only
737
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