NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 118

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.50
5.1.51
5.1.52
118
PVCCTL—Port VC Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
VC0RCAP—VC0 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
VC0RCTL—VC0 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Controls the resources associated with PCI Express Virtual Channel 0.
31:16
30:27
26:24
15:4
14:0
3:1
Bit
Bit
Bit
15
31
0
Access &
Access &
Access &
Default
Default
Default
000 b
000 b
R/W
RO
0 b
RO
1 b
RO
Reserved
VC Arbitration Select
This field will be programmed by software to the only possible value as indicated in
the VC Arbitration Capability field. The value 001b when written to this field will
indicate the VC arbitration scheme is hardware fixed (in the root complex).
This field can not be modified when more than one VC in the LPVC group is enabled.
Reserved
Reserved
Reject Snoop Transactions
0: Transactions with or without the No Snoop bit set within the TLP header are
1: Any transaction without the No Snoop bit set within the TLP header will be
Reserved
VC0 Enable
For VC0 this is hardwired to 1 and read only as VC0 can never be disabled.
Reserved
VC0 ID
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only.
allowed on this VC.
rejected as an Unsupported Request.
1
10Ch
0000h
R/W
16 bits
1
110h
00000000h
RO
32 bits
1
114h
800000FFh
RO, R/W
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Host-PCI Express Bridge Registers (D1:F0)