NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 56

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.16
4.1.17
56
DEVEN—Device Enable (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register allows for enabling/disabling of PCI devices and functions that are within
the MCH.
DEAP - DRAM Error Address Pointer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register contains the address of detected DRAM ECC error(s).
31:3
31:7
6:1
Bit
Bit
2
1
0
0
Access &
Access &
0000000h
Default
Default
R/W
R/W
RO/S
RO/S
1 b
RO
1 b
1b
0b
Reserved
Intel® 3010 chipset only:
PCI Express Port (D3EN):
0: Bus 0 Device 3 Function 0 is disabled and hidden.
1: Bus 0 Device 3 Function 0 is enabled and visible.
BIOS Requirement: The link must be disabled (see Dev 3 B0h[4]) prior to the
device being disabled.
On Intel® 3000 chipset, this bit is Reserved.
PCI Express Port (D1EN):
0: Bus 0 Device 1 Function 0 is disabled and hidden.
1: Bus 0 Device 1 Function 0 is enabled and visible.
Device 1 must not be disabled when Device 3 is enabled.
BIOS Requirement: The link must be disabled (see Dev 1 B0h[4]) prior to the
device being disabled.
Host Bridge: Hardwired to 1. Bus 0 Device 0 Function 0 may not be disabled.
Error Address Pointer (EAP): This field is used to store the 128B (Two Cache
Line) address of main memory for which an error (single bit or multi-bit error) has
occurred. The address is captured after any address remapping through
REMAPBASE/ REMAPLIMIT is applied, such that all physical system memory
appears as a contiguous logical address block. It is valid to compare this address
against C0DRB* and C1DRB* registers to determine which rank of memory failed.
Note that the value of this bit field represents the address of the first single or the
first multiple bit error occurrence after the error flag bits in the ERRSTS Register
have been cleared by software. A multiple bit error will overwrite a single bit error.
Once the error flag bits are set as a result of an error, this bit field is locked and
doesn't change as a result of a new error. These bits are reset on PWROK.
Reserved
Channel Indicator (CHI): This bit indicates which memory channel had the
error.
0
54-57h
00000003h
R/W
32 bits
0
58-5Bh
00000000h
RO/S;
32 bits
0: Channel 0
1: Channel 1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description