NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 155

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

System Address Map
8.4.5
8.5
Note:
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
of the PCI Express root complex hierarchy. This range will be aligned to a 64 MB, 128
MB or 256 MB boundary. BIOS must assign this address range such that it will not
conflict with any other address ranges.
PCI Express
The MCH can be programmed to direct memory accesses to the PCI Express interface
when addresses are within either of two ranges specified via registers in MCH’s Device
#1 configuration space.
The MCH positively decodes memory accesses to PCI Express memory address space
as defined by the following inequalities:
It is essential to support a separate Prefetchable range in order to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
Note that the MCH Device #1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express that
require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the device 1 PCICMD1
register to enable the memory base/limit and prefetchable base/limit windows.
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and
Top of Memory Segment (TSEG). System Management RAM space provides a memory
area that is available for the SMI handlers and code and data storage. This memory
resource is normally hidden from the system OS so that the processor has immediate
access to this memory space upon entry to SMM. The MCH provides three SMRAM
options:
DMI and PCI Express masters are not allowed to access the SMM space.
• The first range is controlled via the Memory Base Register (MBASE) and Memory
• The second range is controlled via the Prefetchable Memory Base (PMBASE) and
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size.
• The above 1 MB solutions require changes to compatible SMRAM handlers’ code to
Limit Register (MLIMIT) registers.
Prefetchable Memory Limit (PMLIMIT) registers.
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤
Prefetchable_Memory_Limit_Address
cacheable SMRAM.
properly execute above 1 MB.
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