NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 53

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.13
Note:
4.1.14
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
MCHBAR—MCH Memory Mapped Register Range Base
Address (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the MCH Memory Mapped Configuration space. There is no
physical memory within this 16 KB window that can be addressed. The 16 KB space
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space.
On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN.
PCIEXBAR—PCI Express Register Range Base Address
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express hierarchy associated with the MCH. There is
not actual physical memory within this window of up to 256 MB that can be addressed.
The actual length is determined by a field in this register. Each PCI Express hierarchy
requires a PCI Express BASE register. The MCH supports one PCI Express hierarchy.
The region reserved by this register does not alias to any PCI 2.3 compliant memory
mapped space. For example MCHBAR reserves a 16 KB space outside of PCIEXBAR
space. It cannot be overlaid on the space reserved by PCIEXBAR for device 0.
On reset, this register is disabled and must be enabled by writing a 1 to the enable field
in this register. This base address shall be assigned on a boundary consistent with the
number of buses (defined by the Length field in this register), above TOLUD and still
within total 36 bit addressable memory space.
31:14
13:1
Bit
0
Access &
Default
00000 h
R/W
R/W
0b
MCH Memory Mapped Base Address:
This field corresponds to bits 31 to 14 of the base address MCH Memory Mapped
configuration space.
BIOS will program this register resulting in a base address for a 16 KB block of
contiguous memory address space. This register ensures that a naturally aligned
16 KB space is allocated within total addressable memory space of 8 GB.
System Software uses this base address to program the MCH Memory Mapped
register set.
Reserved
MCHBAR Enable (MCHBAREN):
0: MCHBAR is disabled and does not claim any memory
1: MCHBAR memory mapped accesses are claimed and decoded appropriately
0
44-47h
00000000h
R/W
32 bits
0
48-4Bh
E0000000h
R/W
32 bits
Description
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