NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 45

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4
Warning:
Note:
Table 4-1.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers
(Device 0, Function 0)
This chapter contains the host bridge registers that are in Device 0 (D0), Function 0
(F0). The DRAM Controller registers are in D0:F0.
D0:F0; registers are listed by address offset in ascending order.
detailed bit descriptions of the registers listed in
in the PCI 2.3 specification, but are not necessary or implemented in this component
are not included in this document.
Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved address locations may return non-zero values. Writes to reserved
locations may cause system failures.
Throughout this document, Device 3 is for Intel® 3010 chipset only.
Host Bridge Register Address Map (D0:F0) (Sheet 1 of 2)
Address
2C-2Dh
58–5Bh
00-01h
02-03h
04-05h
06-07h
09-0Bh
0F-2Bh
30-33h
40-43h
44-47h
48-4Bh
4C-4Fh
50-53h
54-57h
Offset
2E-2Fh
35-3Fh
0Ch
0Dh
08h
0Eh
34h
Register Symbol
PCIEXBAR
MCHBAR
DMIBAR
PCICMD
CAPPTR
PCISTS
DEVEN
EPBAR
SVID
DEAP
HDR
DID
MLT
VID
RID
SID
CC
—
—
—
—
—
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Reserved
Master Latency Timer
Header Type
Reserved
Subsystem Vendor
Identification
Subsystem Identification
Reserved
Capabilities Pointer
Reserved
Egress Port Base Address
MCH Memory Mapped
Register Range Base
Address
PCI Express Register
Range Base Address
Root Complex Register
Range Base Address
Reserved
Device Enable
DRAM Error Address
Register Name
Table
Table 4-1
4-1. All registers that are defined
Default Value
is an address map for
00000000h
00000000h
E0000000h
00000000h
00000003h
00000000h
060000h
8086h
2778h
0006h
0090h
0000h
0000h
C0h
00h
00h
E0h
—
—
—
—
—
Section 4.1
provides
RO, R/WC
RO, R/W
Access
R/WO
R/WO
RO/S
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
—
—
—
—
—
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