NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 58

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.20
Warning:
58
PAM0—Programmable Attribute Map 0 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h-0FFFFFh
The MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map
(PAM) Registers are used to support these features. Cache ability of these areas is
controlled via the MTRR registers in the P6 processor. Two bits are used to specify
memory attributes for each memory segment. These bits apply to both host accesses
and PCI initiator accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory
segment are claimed by the MCH and directed to main memory. Conversely, when RE =
0, the host read accesses are directed to PRIMARY PCI.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main memory. Conversely,
when WE = 0, the host write accesses are directed to PRIMARY PCI.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only.
Each PAM Register controls two regions, typically 16 KB in size.
The MCH may hang if a PCI Express or DMI originated access to Read Disabled or Write
Disabled PAM segments occur (due to a possible IWB to non-DRAM). For these reasons
the following critical restriction is placed on the programming of the PAM regions:
At the time that a DMI or PCI Express accesses to the PAM region may occur, the
targeted PAM segment must be programmed to be both readable and writeable.
7:6
5:4
3:0
Bit
Access &
Default
00 b
R/W
Reserved
0F0000-0FFFFF Attribute (HIENABLE): This field controls the steering of read
and write cycles that addresses the BIOS area from 0F0000 to 0FFFFF.
Reserved
0
90h
00h
R/W
8 bits
00:DRAM Disabled: All accesses are directed to the DMI.
01:Read Only: All reads are sent to DRAM. All writes are forwarded
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
to the DMI.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description