NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 41

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

MCH Register Description
3.4.1
3.4.2
3.4.2.1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Internal Device Configuration Accesses
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus #0 device.
If the targeted PCI Bus #0 device exists in the MCH and is not disabled, the
configuration cycle is claimed by the appropriate device.
Bridge Related Configuration Accesses
Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs
(Transaction Layer Packets):
And special fields for this type of TLP:
See the PCI Express specification for more information on both the PCI 2.3 compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
PCI Express Configuration Accesses
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access matches the Device #1 or #3 Secondary Bus Number, a
PCI Express Type 0 Configuration TLP is generated on the PCI Express link targeting the
device directly on the opposite side of the link. This should be Device #0 on the bus
number assigned to the PCI Express link (likely Bus #1).
The device on other side of link must be Device #0. The MCH will Master Abort any
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but does not match the Device #1 or
#3 Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
PCI Express Configuration Writes:
• Internally, the host interface unit translates writes to PCI Express extended
• Writes to extended space are posted on the FSB, but non-posted on the PCI
Bus Number [7:0] is Header Byte 8 [7:0]
Device Number [4:0] is Header Byte 9 [7:3]
Function Number [2:0] is Header Byte 9 [2:0]
Extended Register Number [3:0] is Header Byte 10 [3:0]
Register Number [5:0] is Header Byte 11 [7:2]
configuration space to configuration writes on the backbone.
Express or DMI (i.e. translated to configuration writes)
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