NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 71

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.2
Table 4-2.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
MCHBAR Configuration Register Details
The MCHBAR registers are offset from the MCHBAR base address.
address map of the registers listed by address offset in ascending order. Detailed bit
descriptions of the registers follow the table.
MCHBAR Register Address Map
1A0–1A3h
1A4–1A7h
10E–10Fh
114–117h
120–123h
124–127h
18E–18Fh
194–197h
F10–F13h
F14–F17h
Address
Offset
10Ch
18Ch
100h
101h
102h
103h
108h
109h
180h
181h
182h
183h
188h
189h
C0DCLKDIS
C1DCLKDIS
C0BNKARC
C1BNKARC
Register
Symbol
C0DRC0
C0DRC1
C1DRC0
C1DRC1
C0DRB0
C0DRB1
C0DRB2
C0DRB3
C0DRA0
C0DRA2
C0DRT1
C1DRB0
C1DRB1
C1DRB2
C1DRB3
C1DRA0
C1DRA2
C1DRT1
PMCFG
PMSTS
Channel 0 DRAM Rank Boundary Address 0
Channel 0 DRAM Rank Boundary Address 1
Channel 0 DRAM Rank Boundary Address 2
Channel 0 DRAM Rank Boundary Address 3
Channel 0 DRAM Rank 0,1 Attribute
Channel 0 DRAM Rank 2,3 Attribute
Channel 0 DRAM Clock Disable
Channel 0 DRAM Bank Architecture
Channel 0 DRAM Timing Register 1
Channel 0 DRAM Controller Mode 0
Channel 0 DRAM Controller Mode 1
Channel 1 DRAM Rank Boundary Address 0
Channel 1 DRAM Rank Boundary Address 1
Channel 1 DRAM Rank Boundary Address 2
Channel 1 DRAM Rank Boundary Address 3
Channel 1 DRAM Rank 0,1 Attribute
Channel 1 DRAM Rank 2,3 Attribute
Channel 1 DRAM Clock Disable
Channel 1 Bank Architecture
Channel 1 DRAM Timing Register 1
Channel 1 DRAM Controller Mode 0
Channel 1 DRAM Controller Mode 1
Power Management Configuration
Power Management Status
Register Name
4000280_00ss_h
Default Value
Table 4-2
02483D22h
02903D22h
00000000h
00000000h
00000000h
00000000h
00000000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
provides an
R/WC/S
Access
R/W/L
R/W/L
R/W,
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
71