NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 43

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

MCH Register Description
3.5.1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
Size:
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or
Word reference will “pass through” the Configuration Address Register and DMI onto
the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus
Number, Device Number, Function Number, and Register Number for which a
subsequent configuration access is intended.
30:24
23:16
15:11
10:8
7:2
1:0
Bit
31
Access &
Default
000b
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
0b
Configuration Enable (CFGE)
1 = Enable. Accesses to PCI configuration space are enabled.
0 = Disable.
Reserved
Bus Number
If the Bus Number is programmed to 00h the target of the Configuration Cycle is a
PCI Bus #0 agent. If this is the case and the MCH is not the target (i.e. the device
number is ≥ 2), then a DMI Type 0 Configuration Cycle is generated.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by
device 1 or 3’s SECONDARY BUS NUMBER or SUBORDINATE BUS NUMBER Register,
then a DMI Type 1 Configuration Cycle is generated.
If the Bus Number is non-zero and matches the value programmed into the
SECONDARY BUS NUMBER Register of device 1 or 3, a Type 0 PCI configuration
cycle will be generated on PCI Express.
If the Bus Number is non-zero, greater than the value in the SECONDARY BUS
NUMBER register of device 1 or 3 and less than or equal to the value programmed
into the SUBORDINATE BUS NUMBER Register of device 1 or 3 a Type 1 PCI
configuration cycle will be generated on PCI Express.
This field is mapped to byte 8 [7:0] of the request header format during PCI Express
Configuration cycles and A[23:16] during the DMI Type 1 configuration cycles.
Device Number
This field selects one agent on the PCI bus selected by the Bus Number. When the
Bus Number field is “00” the MCH decodes the Device Number field. The MCH is
always Device Number 0 for the Host bridge entity, Device Number 1 for the Host-
PCI Express entity. Therefore, when the Bus Number =0 and the Device Number
equals 0, 1 or 3 the internal MCH devices are selected.
This field is mapped to byte 6 [7:3] of the request header format during PCI Express
Configuration cycles and A [15:11] during the DMI configuration cycles.
Function Number
This field allows the configuration registers of a particular function in a multi-
function device to be accessed. The MCH ignores configuration cycles to its internal
devices if the function number is not equal to 0.
This field is mapped to byte 6 [2:0] of the request header format during PCI Express
Configuration cycles and A[10:8] during the DMI configuration cycles.
Register Number
This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register.
This field is mapped to byte 7 [7:2] of the request header format during PCI Express
Configuration cycles and A[7:2] during the DMI Configuration cycles.
Reserved
0CF8h-0CFBh Accessed as a DW
00000000h
R/W
32 bits
Description
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