NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 65

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.32
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
ESMRAMC—Extended System Management RAM Control
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
2:0
Bit
Bit
4
3
7
6
5
4
Access &
Access &
Default
Default
R/W/C
R/W/L
R/W/L
R/W/L
010 b
0 b
0 b
RO
0 b
0 b
RO
1 b
RO
1 b
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0
and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN
become read only. D_LCK can be set to 1 via a normal configuration space write but
can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide
convenience with security. The BIOS can use the D_OPEN function to initialize SMM
space and then use D_LCK to "lock down" SMM space in the future so that no
application software (or BIOS itself) can violate the integrity of SMM space, even if
the program has knowledge of the D_OPEN function.
Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM
functions are enabled, providing 128 KB of DRAM accessible at the A0000h address
while in SMM (ADSB with SMM decode). To enable Extended SMRAM function this
bit has be set to 1. Refer to the section on SMM for more details. Once D_LCK is set,
this bit becomes read only.
Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates the
location of SMM space. SMM DRAM is not remapped. It is simply made visible if the
conditions are right to access SMM space, otherwise the access is forwarded to DMI.
Since the MCH supports only the SMM space between A0000h and BFFFFh, this field
is hardwired to 010.
Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space
location (i.e. above 1 MB or below 1 MB) When G_SMRAME is 1 and H_SMRAME is
1, the high SMRAM memory space is enabled. SMRAM accesses within the range
0FEDA0000h to 0FEDBFFFFh are remapped to DRAM addresses within the range
000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR): This bit is set when CPU has accessed the
defined memory ranges in Extended SMRAM (High Memory and T-segment) while
not in SMM space and with the D-OPEN bit = 0. It is software’s responsibility to
clear this bit. The software must write a 1 to this bit to clear it.
SMRAM Cacheable (SM_CACHE): This bit is forced to ‘1’ by the MCH.
L1 Cache Enable for SMRAM (SM_L1): This bit is forced to ‘1’ by the MCH.
0
9Eh
38h
R/W/L, RO
8 bits
Description
Description
65