NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 166

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.12.9
3.8.12.10
166
CORERRMSK[7:2, 0] - Correctable Error Mask
This register masks correctable errors from being signalled. They are still logged in the
CORERRSTS register.
AERRCAPCTRL[7:2, 0] - Advanced Error Capabilities and Control
Register
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
This register identifies the capability structure and points to the next structure.
31:13
11:9
5:1
5:1
Bit
Bit
12
7
6
0
8
7
6
0
RWCST
RWCST
RWCST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
RV
RV
RV
RV
0, 2-3
0
110h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
110h
Intel 5000Z Chipset
4-7
0
110h
Intel 5000P Chipset
0, 2-3
0
114h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
114h
Intel 5000Z Chipset
4-7
0
114h
Intel 5000P Chipset
Default
Default
0h
0
0
0
0h
0h
0h
0
0
0
0
0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
IO14Err: Bad DLLP Status
IO13Err: Bad TLP Status
Reserved
IO12Err: Receiver Error Status
Reserved
IO16Msk: Replay Timer Time-out Mask
Reserved
IO15Msk: Replay_Num Rollover Mask
IO14Msk: Bad DLLP Mask
IO13Msk: Bad TLP Mask
Reserved
IO12Msk: Receiver Error Mask
Description
Description
Register Description