NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 9

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
5-19 Intel 5000P Chipset PCI Express General Purpose Ports ........................................ 345
5-20 PCI Express Packet Visibility By Physical Layer .................................................... 348
5-21 PCI Express Elastic Buffer (x4 Example) ............................................................. 349
5-22 PCI Express Deskew Buffer (4X Example) ........................................................... 350
5-23 PCI Express Packet Visibility By Link Layer.......................................................... 351
5-24 PCI Express Packet Visibility By Transaction Layer ............................................... 354
5-25 Intel 5000P Chipset Power Sequencing ............................................................... 355
5-26 Power-On Reset Sequence................................................................................ 359
5-27 MCH SM Bus Interfaces .................................................................................... 360
5-28 DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
5-29 DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled) ................ 364
5-30 DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC Disabled) ...... 365
5-31 DWORD Memory Write Protocol ......................................................................... 365
5-32 DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
5-33 DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled) ................ 365
5-34 DWORD Memory Read Protocol (SMBus Word Write / Word Read, PEC Disabled)...... 366
5-35 WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled) .................. 366
5-36 SMBus Configuration Read (Block Write / Block Read, PEC Enabled) ....................... 368
5-37 SMBus Configuration Read (Word Writes / Word Reads, PEC Enabled) .................... 369
5-38 SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) ...................... 369
5-39 SMBus Configuration Write (Block Write, PEC Enabled) ......................................... 369
5-40 SMBus Configuration Write (Word Writes, PEC Enabled)........................................ 370
5-41 SMBus Configuration Write (Write Bytes, PEC Enabled)......................................... 370
5-42 Random Byte Read Timing................................................................................ 371
5-43 Byte Write Register Timing ............................................................................... 372
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10-1 Intel 5000P Chipset Quadrant Map..................................................................... 423
10-2 Intel 5000P Chipset MCH Ballout Left Side (Top View) .......................................... 424
10-3 Intel 5000P Chipset MCH Ballout Center (Top View) ............................................. 425
10-4 Intel 5000P Chipset MCH Ballout Right Side (Top View) ........................................ 443
10-5 Intel 5000V Chipset Quadrant Map .................................................................... 444
10-6 Intel 5000V Chipset MCH Ballout Left Side (Top View) .......................................... 445
10-7 Intel 5000V Chipset MCH Ballout Center (Top View) ............................................. 446
10-8 Intel 5000V Chipset MCH Ballout Right Side (Top View) ........................................ 447
10-9 Bottom View................................................................................................... 486
10-10 Top View........................................................................................................ 487
10-11 Package Stackup ............................................................................................. 488
10-12 Notes ............................................................................................................ 489
11-1 Intel 5000Z Chipset Quadrant Map .................................................................... 491
PEC Disabled) ................................................................................................. 364
PEC Disabled) ................................................................................................. 365
PCI Express Hot-Plug/VPP Block Diagram............................................................ 375
Intel 5000V Chipset System Block Diagram......................................................... 402
Intel 5000V SM Bus Interfaces .......................................................................... 403
Simplified TAP Controller Block Diagram ............................................................. 406
TAP Controller State Machine ............................................................................ 407
TAP Instruction Register ................................................................................... 409
TAP Instruction Register Operation .................................................................... 409
TAP Instruction Register Access......................................................................... 410
TAP Data Register ........................................................................................... 411
Bypass Register Implementation ....................................................................... 412
Intel 5000Z Chipset System Block Diagram......................................................... 417
Intel 5000Z Chipset MCH SM Bus Interfaces........................................................ 421
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